1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of forming copper-based conductive structures on semiconductor devices, such as transistors.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of field effect transistors (NMOS and PMOS transistors) that substantially determine performance of the integrated circuits. Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreased in size to enhance the performance of the transistors and the overall functionality of the circuit. Given that the channel length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of additional techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of highly-conductive copper lines and vias to provide electrical wiring connections to the transistors, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors).
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Generally, as the device dimensions have decreased, the physical size of the conductive interconnections, e.g., metal lines and metal vias formed in multiple metallization layers above the device level, have also become smaller. Accordingly, the electrical resistance of conductive interconnections becomes a significant issue in the design of the overall product. Moreover, the reduction in size of the conductive interconnections makes it more difficult to manufacture copper conductive lines and vias without introducing an unacceptable level of voids in the resulting structure.
FIGS. 1A-1B depict portions of an illustrative prior art process flow for forming various illustrative examples of copper conductive structures, e.g., copper lines and vias. FIG. 1A depicts an illustrative device 10 comprised of a layer of insulating material 12, an etch stop layer 14, another layer of insulating material 16, a dielectric hard mask layer 18 and a metal hard mask layer 20. Also depicted in FIG. 1A is a conductive copper structure 22 (with an illustrative barrier layer 22A), e.g., a copper line, positioned in the layer of insulating material 12, and a plurality of openings 24, 26 formed in the depicted stack of materials. The openings 24 expose portions of the conductive copper structure 22. The various layers depicted in FIG. 1A may be comprised of a variety of different materials. For example, the layers of insulating material 12, 16 may be comprised of a low-k material (k value less than about 3.5), the etch stop layer 14 may be comprised of silicon nitride, the hard mask layer 18 may be a TEOS-based layer of silicon dioxide, and the metal hard mask layer 20 may be made of, for example, titanium nitride.
The device 10 depicted in FIG. 1A was subjected to various known processing operations. For example, the conductive copper structure 22 was formed in the first layer of insulating material 12 using known techniques for forming such structures, e.g., damascene techniques. Thereafter, the various layers 14, 16, 18 and 20 were formed on the device 10 using known deposition techniques, e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. Thereafter, the metal hard mask layer 20 was patterned using known photolithographic tools and techniques. Next, using the patterned metal hard mask layer 20 as an etch mask, the openings 24, 26 were formed in the depicted layers of material by performing a plurality of etching processes. FIG. 1A depicts the device 10 after an etching process was performed on the etch stop layer 14 through the openings 24 in the layer of insulating material 16 to thereby expose portions of the underlying conductive copper structure 22.
FIG. 1B depicts the device 10 after a wet etching process has been performed to remove the patterned metal hard mask 20. In the case where the metal hard mask 20 is comprised of titanium nitride, the wet etching process may be performed using diluted hydrogen peroxide (H2O2) or diluted ammonia (NH3OH) and an H2O2 mixture. Unfortunately, the wet etching process performed to remove the metal hard mask 20 also attacks the underlying copper conductive structure 22 resulting in the formation of illustrative voids 30. The voids 30 tend to be non-uniform in nature and also tend to exhibit a significant degree of undercutting in the regions indicated by the arrows 31. As a result of the presence of the voids 30, the formation of conductive copper structures (not shown) in the openings 24 is very difficult and may lead to the formation of voids in any such conductive copper structure. As one example, attempts to form conductive copper structures in the openings 24 typically involve initially performing a deposition process to form a barrier layer (not shown) in the opening 24 and thereafter forming a conductive copper structure above the barrier layer using known electroplating or electroless plating techniques. Unfortunately, due to the presence of the voids 30, and the undercutting caused by such voids 30, the barrier layer cannot reliably fill the voids 30, thereby leaving undesirable voids in the final conductive structure for the device 10.
The present disclosure is directed to various methods of forming copper-based conductive structures on semiconductor devices, such as transistors, that may avoid, or at least reduce, the effects of one or more of the problems identified above.